MRAM devices have become the subject of increasing interest, in view of the discovery of magnetic tunnel junctions having a strong magnetoresistance at ambient temperatures. MRAM devices offer a number of benefits, such as faster speed of writing and reading, non-volatility, and insensitivity to ionizing radiations. Consequently, MRAM devices are increasingly replacing memory devices that are based on a charge state of a capacitor, such as dynamic random access memory devices and flash memory devices.
In a conventional implementation, a MRAM device includes an array of MRAM cells, each one of which includes a magnetic tunnel junction formed of a pair of ferromagnetic layers separated by a thin insulating layer. One ferromagnetic layer, the so-called reference layer, is characterized by a magnetization with a fixed direction, and the other ferromagnetic layer, the so-called storage layer, is characterized by a magnetization with a direction that is varied upon writing Of the device, such as by applying a magnetic field. When the respective magnetizations of the reference layer and the storage layer are antiparallel, a resistance of the magnetic tunnel junction is high, namely having a resistance value Rmax corresponding to a high logic state “1”. On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction is low, namely having a resistance value Rmin corresponding to a low logic state “0”. A logic state of a MRAM cell is read by comparing its resistance value to a reference resistance value Rref, which is derived from a reference cell or a group of reference cells and represents an inbetween resistance value between that of the high logic state “1” and the low logic state “0”.
A MRAM device is conventionally manufactured by photolithography, in which a photoresist is used as a soft mask tier patterning a stack of magnetic layers. Specifically, a photoresist layer is formed on the stack of magnetic layers, and the photoresist layer is then patterned to form an array of dots. Portions of the stack of magnetic layers exposed by the array of dots are then etched away to form a corresponding array of MRAM cells. Subsequently, the photoresist layer is stripped to result in a MRAM device.
The above-described manufacturing method can suffer from certain deficiencies. Specifically, a size of a MRAM cell is typically governed by a resolution of photolithography, thereby presenting challenges in terms of scaling down to achieve higher densities of MRAM cells. Patterning a photoresist layer to form an array of dots with small sizes can be difficult to achieve, without the use of expensive and complex photolithographic equipment and techniques that can result in higher manufacturing costs. Moreover, shapes of resulting MRAM cells can be difficult to control, given the use of a photoresist as a soft mask. Specifically, an array of dots of the photoresist can be prone to striations or other shape imperfections, such as arising from conditions during development or exposure or arising from deformations introduced during etching, given a relatively high etch-rate of the photoresist. Such shape imperfections, in turn, can be imparted onto resulting MRAM cells, resulting in a variability of shapes in an array of the MRAM cells. This variability can impact a resistance of the MRAM cells across the array and can result in a distribution of the resistance values Rmin and Rmax for the array, thereby complicating a comparison between a measured resistance value of an individual cell and a reference resistance value Rref during reading.
It is against this background that a need arose to develop the memory devices and related manufacturing methods described herein.